The Map of Computer Cities
Imagine a busy city of computers. Some machines are small shops run by one worker, others are giant factories with many people building things at the same time. "Architectural classification" is the map that tells us what kind of city a computer is—how its citizens (instructions and data) move, how the buildings (processors and memory) connect, and how many jobs can run side by side.
In Computer Organization & Architecture (COA), this topic sits inside Process Organization, because it explains how the CPU and memory are arranged to handle many tasks. Understanding architectural classification helps us see both the logical flow of information and the physical structure that enables it.
Visualize computers as cities with different layouts and workflows
Shows how instructions, data, processors, and memory are organized
Part of COA that focuses on CPU and memory arrangement
Every computer, no matter how fancy, obeys a rhythm: fetch an instruction, decode it, execute it, and store the result. Picture a librarian (the control unit) fetching one instruction card at a time, a translator (decoder) reading it, and a worker (ALU) doing the job.
The sequence of instructions flowing into the CPU for processing
The flow of data back and forth between the CPU and memory
These two streams are the foundation for classifying computer designs. How these streams flow—singly or in parallel—forms the basis of architectural classification schemes. Understanding this fundamental rhythm helps us see how different computer architectures optimize this cycle for different purposes.
In 1972, Michael Flynn said, "Let's classify computers by how many instruction streams and data streams they can handle." This created a simple but powerful framework that remains influential today.
Single Instruction, Single Data. Think of a single-lane road—classic sequential machines where one instruction operates on one data item at a time.
Single Instruction, Multiple Data. A single traffic light tells many lanes to go at once—great for graphics or vector math where the same operation applies to multiple data items.
Multiple Instructions, Single Data. Rare, like a relay race where many runners work on the same baton. Multiple instructions process the same data stream, often for fault tolerance.
Multiple Instructions, Multiple Data. A bustling city with many independent workers—this is how most modern parallel computers behave, with multiple processors executing different instructions on different data.
Flynn's map shows behavior—the patterns of flow—without worrying about physical layout. It focuses on how many instruction and data streams can be processed simultaneously, providing a high-level view of parallelism in computer systems.
Beyond Flynn's classification, other researchers developed more detailed schemes to capture different aspects of computer architecture.
Feng's classification looks at degree of parallelism—how many bits or words can be processed at once, from bit-by-bit (Word Serial Bit Serial - WSBS) to fully parallel word-and-bit processing (Word Parallel Bit Parallel - WPBP).
Word Serial, Bit Serial - processes one bit at a time, sequentially
Word Parallel, Bit Parallel - processes all bits of multiple words simultaneously
Handler's classification dives into pipeline details, describing how many control units, ALUs, and bit-level circuits can work in parallel or in stages. It uses notations like (p * p', a * a', b * b') to capture how a machine chains operations.
Number of processors and their configuration
Arithmetic Logic Units and their arrangement
Bit-level processing elements and their organization
These classification schemes add finer measurements of parallel power beyond Flynn's simple four boxes. They provide more detailed ways to describe and compare different computer architectures based on their internal organization and processing capabilities.
Behavior is one thing; wiring is another. Architects also sort computers by how their processors and memories are physically connected.
All processors dip into the same memory pool. It's fast and good for real-time work, but everyone must politely share.
Uniform Memory Access - Equal memory access time for all processors
Non-Uniform Memory Access - Each processor has local memory plus slower access to others
Cache Only Memory Access - Everything is cache, forming a global memory space
Each processor has its own memory and talks to others by sending messages—like independent houses connected by a mail service. This avoids memory conflicts but needs careful communication.
Interconnection networks (crossbars, multistage switches) are the "roads" linking processors and memory. The design of these networks significantly impacts system performance and scalability.
Parallelism isn't just hardware; it starts with the program. We look for pieces that can run at the same time:
Tiny instruction chunks (less than ~20 instructions), like assembly-line micro-steps. Offers many parallel tasks but with high coordination overhead.
Procedures or subroutines with hundreds of instructions. Balances parallelism with coordination costs.
Whole programs or large tasks with thousands of instructions. Minimal coordination overhead but fewer parallel opportunities.
Before splitting tasks, we check dependencies:
Does one instruction need another's output? True dependencies prevent parallel execution.
Loops or if/else order that affects which instructions execute. Branches can limit parallelism.
Do tasks fight for the same hardware? Resource conflicts can serialize execution.
Bernstein's conditions give a neat test: two tasks can run in parallel only if they never try to read and write the same memory locations in conflicting ways. This formal approach helps identify parallelizable code sections.
COA wants you to see both behavior (instruction/data flow) and structure (how components connect). Architectural classification ties them together:
Shows the basic CPU rhythm that all architectures follow, whether sequential or parallel. Understanding this cycle is fundamental to seeing how different architectures optimize or parallelize it.
Explain types of parallelism and how they manifest in different architectures
Shows physical organization and how it affects performance and programming models
Teach how software can exploit the hardware by identifying parallelizable code sections
Understanding these schemes helps when you design processors, optimize programs for parallel execution, or choose the right architecture for tasks like AI training or scientific simulation. This knowledge bridges the gap between theoretical computer science and practical engineering.
Seen as a story, architectural classification is the bridge between the logical dance of instructions and the physical city of processors and memory. It tells you not only what a computer does but how its internal society is organized so that countless operations can march—or sprint—together.
| Viewpoint | Key idea | Example |
|---|---|---|
| Instruction/Data Flow (Flynn) | SISD, SIMD, MISD, MIMD | GPU = SIMD, multicore server = MIMD |
| Degree of Parallelism (Feng) | Bits/words processed per time | WPBP fully parallel |
| Pipeline Detail (Handler) | p, a, b notation | Cray-1 = (1, 12*8, 64*(1~14)) |
| Physical Structure | Shared vs. distributed memory | UMA/NUMA/COMA vs. Loosely coupled |
| Software Grain | Fine, medium, coarse | Loop parallelism vs. whole-program |
Architectural classification provides multiple lenses to understand computer systems. By examining both behavior and structure, we gain a comprehensive view of how computers are organized and how they can be optimized for different tasks. This knowledge is essential for computer architects, system programmers, and anyone seeking to understand the fundamental principles that underpin all computing systems.
As computing continues to evolve with new paradigms like quantum computing, neuromorphic architectures, and specialized AI accelerators, classification schemes will also need to adapt. However, the fundamental principles of understanding instruction flow, data access, and physical organization will remain relevant, providing a foundation for understanding whatever comes next in the ever-changing landscape of computer architecture.