Sequential Circuits for Digital Systems
A counter is a sequential digital circuit built using flip-flops.
It stores and counts the number of clock pulses applied to it.
Counters are basically registers that go through a predetermined sequence of states (binary numbers).
Each state (binary value) represents a count.
Each clock pulse increments the counter by 1
Counters are classified mainly into two categories:
Each flip-flop is triggered by the output of the previous flip-flop.
The clock is applied only to the first flip-flop.
Propagation delay accumulates → slower for large bit counters.
Example: 4-bit ripple counter → counts 0 to 15 (0000 → 1111).
Clock is applied to all flip-flops simultaneously.
Faster than ripple counters.
Requires extra logic (AND/OR gates) to control transitions.
Counts in increasing order (0000, 0001, 0010, …).
Counts in decreasing order (1111, 1110, 1101, …).
Can count both up and down based on control input.
A type of shift register counter where a single 1 circulates.
A modified ring counter where complement feedback is used.
Uses 3 flip-flops (Q2, Q1, Q0).
Counts from 000 → 111 (0 to 7 in decimal).
After 111, it rolls back to 000 (modulo-8 counter).
| Clock Pulses | Q2 | Q1 | Q0 | Decimal Count |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 1 |
| 2 | 0 | 1 | 0 | 2 |
| 3 | 0 | 1 | 1 | 3 |
| 4 | 1 | 0 | 0 | 4 |
| 5 | 1 | 0 | 1 | 5 |
| 6 | 1 | 1 | 0 | 6 |
| 7 | 1 | 1 | 1 | 7 |
Keeps track of the address of the next instruction.
To count number of executed instructions.
Divide clock frequency by 2, 4, 8… for timing.
Detecting and counting input pulses (e.g., in I/O devices).
Counters generate addresses sequentially in RAM/ROM.
A counter in COA is a hardware sequential circuit made from flip-flops that counts clock pulses in binary form. They are crucial for instruction sequencing, timing, and event counting in computer systems.
A counter is a sequential circuit (made from flip-flops) that counts the number of clock pulses applied to it.
Each clock pulse changes the counter's state.
The states are represented in binary form.
Counters are widely used in timers, frequency dividers, program counters, event counting, and digital clocks.
A counter is like a digital "pulse counter" that goes 0 → 1 → 2 → … depending on clock inputs.
Called ripple because the clock "ripples" from one flip-flop to the next.
Only the first flip-flop gets the external clock pulse.
Each subsequent flip-flop is triggered by the output of the previous one.
This creates a propagation delay (because the clock signal travels step-by-step).
Simpler design, but slower for large bit counters.
Components: Two T flip-flops (or JK flip-flops with J=K=1).
QA = 0, QB = 0. (binary = 00)
FF-A toggles → QA = 1.
FF-B sees QA=1 as a clock, but since it is negative-edge triggered, it does not toggle yet.
Result: QA = 1, QB = 0 (binary = 01)
FF-A toggles → QA = 0.
This falling edge of QA acts as a clock for FF-B → toggles QB = 1.
Result: QA = 0, QB = 1 (binary = 10)
FF-A toggles → QA = 1.
QB remains unchanged (still 1).
Result: QA = 1, QB = 1 (binary = 11)
FF-A toggles → QA = 0.
This falling edge toggles FF-B back to 0.
Result: QA = 0, QB = 0 (binary = 00 → back to start)
So, the counter cycles through: 00 → 01 → 10 → 11 → 00.
This is a mod-4 counter (counts 4 states).
In this design, all flip-flops receive the same clock pulse simultaneously.
No "rippling" delay → much faster.
Requires extra logic to ensure that each flip-flop toggles at the right time.
Clock signal goes directly to both FF-A and FF-B.
FF-A is always toggled (J=K=1).
FF-B toggles only when QA = 1 (controlled by logic gates).
QA = 0, QB = 0 (binary = 00)
FF-A toggles → QA = 1.
FF-B stays unchanged (QB = 0).
Result: QA = 1, QB = 0 (binary = 01)
FF-A toggles → QA = 0.
Since QA=0 before toggle, logic makes FF-B toggle → QB = 1.
Result: QA = 0, QB = 1 (binary = 10)
FF-A toggles → QA = 1.
FF-B stays 1.
Result: QA = 1, QB = 1 (binary = 11)
FF-A toggles → QA = 0.
Logic toggles FF-B → QB = 0.
Result: QA = 0, QB = 0 (binary = 00 → back to start)
Again, sequence is 00 → 01 → 10 → 11 → 00, but much faster than asynchronous because all flip-flops are clocked together.
| Feature | Asynchronous (Ripple) | Synchronous |
|---|---|---|
| Clock Input | Only 1st flip-flop gets external clock | All flip-flops get clock simultaneously |
| Speed | Slower (propagation delay) | Faster (no delay) |
| Complexity | Simple design | More complex (requires gating logic) |
| Use Cases | Simple low-speed counters | High-speed counters in CPUs & digital circuits |